 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HM5116100B Series 16,777,216-word x 1-bit Dynamic Random Access Memory ADE-203-371A (Z) Rev. 1.0 Nov. 10, 1995 Description The Hitachi HM5116100B is a CMOS dynamic RAM organized 16,777,216-word x 1-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5116100B offers Fast Page Mode as a high speed access mode. Features * Single 5 V (10%) * High speed Access time: 60 ns/ 70 ns/ 80 ns (max) * Low power dissipation Active mode: 40 mW/385 mW/358 mW (max) Standby mode 11 mW (max) * Fast page mode capability * Long refresh period 4096 refresh cycles : 64 ms * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * Test function 16-bit parallel test mode Ordering Information Type No. HM5116100BS-6 HM5116100BS-7 HM5116100BS-8 Access Time 60 ns 70 ns 80 ns Package 300-mil 26-pin plastic SOJ (CP-26/24DB) This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS. HM5116100B Series Pin Arrangement HM5116100BS Series VCC Din NC WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS Dout NC CAS NC A9 A10 A0 A1 A2 A3 V CC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin Name A0 to A11 A0 to A11 Din Dout RAS CAS WE VCC VSS NC Function Address input Refresh address input Data input Data output Row address strobe Column address strobe Read/write enable Power supply (+5 V) Ground No connection 2 HM5116100B Series Block Diagram RAS Dout Dout Buffer CAS WE Din Din Buffer Column decoder & driver Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Peripheral Circuit Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Row decoder & driver Selector Selector Selector Row decoder & driver Selector Column decoder & driver Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Row decoder & driver Selector Selector Selector Address A0 to A11 Selector Row decoder & driver 3 HM5116100B Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Note: 1. All voltage referred to VSS Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 4 HM5116100B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM5116100B -6 Parameter Operating current Standby current *1, *2 -7 Max Min 80 2 -- -- -8 Max Min 70 2 -- -- Max Unit Test Conditions 65 2 mA mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC - 0.2V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA Symbol Min I CC1 I CC2 -- -- -- 1 -- 1 -- 1 mA RAS-only refresh current*2 Standby current *1 I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 80 5 80 70 10 10 VCC 0.4 -- -- -- -- -10 -10 2.4 0 70 5 70 60 10 10 VCC 0.4 -- -- -- -- -10 -10 2.4 0 65 5 65 50 10 10 VCC 0.4 mA mA mA mA A A V V CAS-before-RAS refresh current Fast page mode current *1, *3 Input leakage current Output leakagecurrent Output high voltage Output low voltage Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address, Data-in) Input capacitance (Clocks) Output capacitance (Data-out) Symbol CI1 CI2 CO Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Booton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 5 HM5116100B Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *16 Test Conditions * Input rise and fall time : 5 ns * Input timing reference levels : 0.8 V, 2.4 V * Output load : 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116100B -6 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD 110 40 10 60 15 0 10 0 10 20 15 15 60 5 3 Max -- -- -- -7 Min 130 50 10 Max -- -- -- -8 Min 150 60 10 Max -- -- -- Unit Notes ns ns ns 10000 70 10000 18 -- -- -- -- 45 30 -- -- -- 50 0 10 0 15 20 15 18 70 5 3 10000 80 10000 20 -- -- -- -- 52 35 -- -- -- 50 0 10 0 15 20 15 20 80 5 3 10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- 50 ns ns ns ns ns ns ns ns ns ns 5 3 4 RAS to column address delay time t RAD t RSH t CSH t CRP tT 6 HM5116100B Series Read Cycle HM5116100B -6 Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output buffer turn-off time Symbol Min t RAC t CAC t AA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OFF -- -- -- 0 0 0 30 30 0 3 -- Max 60 15 30 -- -- -- -- -- -- -- 15 -7 Min -- -- -- 0 0 0 35 35 0 3 -- Max 70 18 35 -- -- -- -- -- -- -- 15 -8 Min -- -- -- 0 0 0 40 40 0 3 -- Max 80 20 40 -- -- -- -- -- -- -- 15 Unit Notes ns ns ns ns ns ns ns ns ns ns ns 11 10 10 6, 7, 17 7, 8, 15, 17 7, 9, 15, 17 Write Cycle HM5116100B -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- -8 Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 13 13 12 7 HM5116100B Series Read-Modify-Write Cycle HM5116100B -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Symbol Min t RWC t RWD t CWD t AWD 130 60 15 30 Max -- -- -- -- -7 Min 153 70 18 35 Max -- -- -- -- -8 Min 175 80 20 40 Max -- -- -- -- Unit Notes ns ns ns ns 12 12 12 Refresh Cycle HM5116100B -6 Parameter Symbol Min 5 10 0 10 0 Max -- -- -- -- -- -7 Min 5 10 0 10 0 Max -- -- -- -- -- -8 Min 5 10 0 10 0 Max -- -- -- -- -- Unit Notes ns ns ns ns ns CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle WE hold time (CBR refresh cycle) RAS precharge to CAS hold time t CHR WE setup time (CBR refresh cycle) t WRP t WRH t RPC Fast Page Mode Cycle HM5116100B -6 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge Symbol Min t PC t RASP t CPA 40 -- -- 35 Max -- -7 Min 45 Max -- -8 Min 50 Max -- Unit Notes ns 14 7, 15, 17 100000 -- 35 -- -- 40 100000 -- 40 -- -- 45 100000 ns 45 -- ns ns RAS hold time from CAS precharge t CPRH 8 HM5116100B Series Fast Page Mode Read-Modify-Write Cycle HM5116100B -6 Parameter Fast page mode read-modify-write cycle time Symbol Min t PRWC 60 35 Max -- -- -7 Min 68 40 Max -- -- -8 Min 75 45 Max -- -- Unit Notes ns ns 12 WE delay time from CAS precharge t CPW Test Mode Cycle *16 HM5116100B -6 Parameter Test mode WE setup time Test mode WE hold time Symbol Min t WTS t WTH 0 10 Max -- -- -7 Min 0 10 Max -- -- -8 Min 0 10 Max -- -- Unit Notes ns ns Counter Test Cycle HM5116100B -6 Parameter Symbol Min 20 Max -- -7 Min 30 Max -- -8 Min 30 Max -- Unit Notes ns CAS precharge time in counter test t CPT cycle Refresh Cycle Parameter Refresh period Symbol t REF Max 64 Unit ms Note 4096 cycles 9 HM5116100B Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assume that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. Assume that tRCD tRCD (max) and tRAD tRAD (max). 9. Assume that tRCD tRCD (max) and tRAD tRAD (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD t CWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 13. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 14. t RASP defines RAS pulse width in fast page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0, CA1, CA10 and CA11 for the 16M x 1 are don't care during test mode. Test mode is set by performing a WE-andCAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 16 bits in parallel at Din and read out from Dout. If 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CAS-beforeRAS refresh cycle or RAS-only refresh cycle. 17. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. XXX: H or L (H: V IH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout 10 HM5116100B Series Timing Waveforms*18 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t RAH t ASC t RAL t CAL t CAH Address Row Column t RRH t RCS t RCH WE t CAC t AA t RAC t OH t OFF , t CLZ Dout Dout 11 HM5116100B Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 12 HM5116100B Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t CWL t RWL t RCS t WP WE t DS t DH Din Din t CLZ t OFF Dout Invalid Dout 13 HM5116100B Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row Column t RCS t CWD t AWD t RWD t WP t CWL t RWL WE t DS t DH Din t CAC t AA t RAC Din t OH t OFF t CLZ Dout 14 Dout HM5116100B Series RAS-Only Refresh Cycle t RC t RAS RAS t RP tT t CRP t RPC t CRP CAS t ASR t RAH Address Row t OFF Dout High-Z * Refresh Address A0 - A11 (RA0 - RA11) CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR tT t CHR t RPC t CRP CAS t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 15 HM5116100B Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RP t RAS t RC t RP RAS tT t RSH t RCD t CHR t CRP CAS t RAD t ASR Address t RAH t ASC t RAL t CAH Column Row t RCS t WRP t RRH t WRH t WRP t WRH WE t CAC , t AA t RAC t CLZ Dout 16 t OH t OFF Dout HM5116100B Series Fast Page Mode Read Cycle t RASP t CPRH RAS t RP tT t CSH t RCD CAS t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t ASR t RAD t RAH t ASC t CAL t CAH t ASC t CAL t CAH t ASC t RAL t CAL t CAH Address Row Column 1 Column 2 t RCS Column N t RCS tRRH tRCH t RCS t RCH t RCH WE t CAC t AA t RAC t CPA t AA t OH t OFF t CAC t CLZ t OH t OFF t CPA t AA , , , t CAC t CLZ t CLZ t OH t OFF Dout Dout 1 Dout 2 Dout N 17 HM5116100B Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z** * t WCS t WCS (min) 18 HM5116100B Series Fast Page Mode Delayed Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 t CWL t RCS t WP Column 2 t CWL t RCS t WP Column N t RWL t CWL t RCS t WP WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N t CLZ t OFF t CLZ t OFF t CLZ Dout Invalid Dout Invalid Dout t OFF Invalid Dout 19 HM5116100B Series Fast Page Mode Read-Modify-Write Cycle t RASP t RP RAS tT t RCD t CAS t CP t PRWC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAD t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row t RCS t RWD Column 1 t RCS t AWD t CWL Column 2 t CWL t AWD t WP t WP t CWD Column N t RCS t AWD t WP t CWD t RWL t CWL WE t CWD t DS t DH t CPW t DS t DH t CPW t DS t DH * Din Din 1 Din 2 Din N t CAC t CAC t CAC t AA t CPA t AA t CPA t AA t RAC t OH t OH t OH t OFF t CLZ t OFF t CLZ t OFF t CLZ Dout Dout 1 Dout 2 Dout N 20 HM5116100B Series Test Mode Cycle*16 *,** Reset Cycle Set Cycle** Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din: H or L 21 HM5116100B Series Test Mode Set Cycle t RC t RP t RAS t RP RAS tT CAS t CP t WTS t WTH WE Address t OFF High-Z Dout 22 SP C@ ,, S R P C B @ t CP t RPC t CSR t CHR t RPC t CRP HM5116100B Series Package Dimensions HM5116100BS Series (CP-26/24DB) 16.90 17.27 Max 21 19 Unit: mm 26 14 1 3.50 0.26 68 0.74 13 8.51 0.13 7.62 0.13 1.30 Max 0.43 0.10 0.10 2.54 1.27 0.80 6.71 0.25 2.65 0.12 +0.25 -0.17 23 |
Price & Availability of HM5116100BSERIES
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |